1. Field of the Invention
The present invention relates to the field of direct bonded wafers, and more particularly, to the field of direct bonded wafers useful in the semiconductor arts.
2. Prior Art
Semiconductor-on-insulator (SOI) devices are attractive because of the high isolation provided between adjacent devices by the insulating substrate. Such devices were suggested more than 20 years ago and silicon-on-sapphire technology in which single crystalline silicon was grown on single crystalline sapphire substrates provided some of the expected benefits. However, the single crystalline silicon grown on sapphire never achieved the high quality provided by wafers sliced from boules of single crystalline silicon grown from silicon melts. Partially as a consequence of that inferior quality of the single crystalline silicon, silicon-on-sapphire devices never lived up to early expectations.
Relatively thick semiconductor wafers having PN junctions disposed at great depth from the wafer surface are required in order to produce high voltage power devices capable of holding off voltages in excess of several thousand volts. Fabrication of devices of this type using conventional fabrication techniques are extremely time consuming because of the great depth to which junctions must be diffused.
Direct bonding of two silicon wafers to each other has been reported. However, those direct bonded wafers have had numerous voids of varying sizes distributed across their bonded interface. Such voids make the composite wafers unusable for SOI device fabrication because when one of the original wafers is thinned (after direct bonding) to the thickness desired for the active devices, the thinned wafer bubbles or bulges at the voids thereby increasing the volume of the void and creating a non-planar surface which is not acceptable for device fabrication. The presence of voids at the bonded interface also renders these prior art direct bonded wafers inappropriate for the fabrication of high voltage devices because the voids would interfere with current flow vertically through the composite wafer perpendicular to the bonded interface.
Consequently, a technique for direct bonding wafers in a void free manner is needed.